(a). Field of the Invention
The present invention relates to a differential amplifier having a reduced current dissipation, and more particularly, to a differential amplifier suitable for use in an input interface of a memory device,
(b). Description of the Related Art
Along with the recent development of the operational speed of microprocessors for use in workstations and personal computers, a dynamic random access memory (DRAM), which is one of peripheral devices for the microprocessors, is required to operate at a higher frequency as high as 100 MHz or more. A synchronous DRAM (SDRAM) operable in synchrony with an external clock signal is known as one of the higher operational speed memories.
Thus, an input interface for use in a memory device as a first stage amplifier which receives external signals to transmit the same after converting to a voltage level for the memory device is also required to operate at a higher speed. LVTTL standard is known as a conventional international standard specifying the input signal level of the input interfaces. FIG. 1 is a graph of the input signal level specified in the LVTTL standard, wherein +0.8 volts to +2.0 volts for an input signal amplitude is specified. The input signal amplitude is generally unchanged in the LVTTIL standard even if the source voltage is changed. In this configuration, the input reference voltage Vref is determined at the median between 0.8 and 2.0 volts, namely, at 1.4 volts by designers for the input interface.
For a higher operational speed, it is required more recently to shift the standard of the input signal amplitude from the conventional LVTTL standard to a new SSTL standard which specifies smaller input signal amplitudes. Thus, input receivers of the input interfaces are requested for satisfying both the LVTIT and SSTL standards during the transition period of the standard.
FIG. 2 is a graph of the input signal amplitude specified in the SSTL standard, wherein the specification of the reference voltage Vref is introduced along with the level of the input signal amplitude, although Vref is not specified in the LVTTL standard The reference voltage Vref varies while keeping the relationship of Vref=0.45.times.Vcc with the external source voltage Vcc. The level for the input signal amplitude is provided therein such that L-level is specified at -0.4 volts from Vref and H-level is specified at +0.4 volts from Vref for a transient change, whereas L-level is specified at -0.2 volts from Vref and H-level is specified at +0.2 volts from Vref for a stationary change.
A conventional input interface adapted to the LVTTL standard uses a differential amplifier such as shown in FIG. 3. The differential amplifier used in a SDRAM comprises: an N-channel transistor Q71 having a gate for receiving an external input signal Vin and a source connected to ground (GND); an N-channel transistor Q70 having a gate for receiving the reference voltage Vref generated in the SDRAM and a source connected to GND; a P-channel transistor Q75 having a gate and a drain connected together to the drain of transistor Q70 at a node 700, and a source connected to a power source line Vcc; and a P-channel transistor Q76 having a drain connected to the drain of transistor Q71, a gate connected to the gate and the drain of transistor Q71 and a source connected to power source line Vcc.
As shown in FIG. 1, the amplitude of input signal Vin is +0.8 to +2.0 volts in the LVTTL standard, and accordingly, reference voltage Vref is set at 1.4V which is the median voltage between H-level and L-level. That is, Vin=Vref.+-.0.6V.
The gate widths "W" as well as the gate lengths "L" are equal between N-channel transistors Q70 and Q71. Similarly, "W" and "L" are respectively equal between P-channel transistors Q75 and Q76. The currents flowing through transistors Q70, Q71, Q75 and Q76 are represented by i70, i71, i75 and i76, respectively.
Since reference voltage Vref is input to the gate of transistor Q70, the drain of which is connected to the drain of transistor Q75 at node 700, i75 and i70 are equal and constitute a constant current. Transistor Q75 and transistor Q76 form a current mirror, thus i75=i76.
If input voltage Vin is equal to the reference voltage Vref in the differential circuit of FIG. 3, then i71=i76=i70 so that the following relationship holds: EQU i70=i75=i76=i71=ia (where Vin=Vref) (1),
wherein ia is a constant current. The output node Vout connecting drains of transistors Q71 and Q76 together is connected to the input of an inverter I1.
FIG. 4 is a signal timing chart of the conventional differential amplifier of FIG. 3. Input signal Mm stays at L-level during time interval T1, rises from L-level to H-level during T2, stays at H-level during T3, falls from H-level to L-level during T4, and again stays at L-level during T5.
During time intervals T1 and T5 where input signal Vin assumes L-level in a stationary state, input signal Vin is lower than reference voltage Vref. Thus, the gate-source voltage Vgs of transistor Q71 is lower than the gate-source voltage Vgs of transistor Q70, and current i71 is smaller than current i70. The equality of the gate-source voltage Vgs of transistor Q76 and the gate-source voltage Vgs of transistor Q75 signifies the equality of currents i76 and i75.
Accordingly, during time intervals T1 and T5, if i71=ib wherein ib is a constant current, the following relationship holds: EQU i70=i75=i76=ia&gt;i71=ib (2).
With reference to relationship (1) as noted above, the current (or current gain of the differential amplifier) for charging the gate capacitance of inverter I1 during the rise of the input voltage Vin is expressed by: EQU i76-i71=ia-ib (3).
By the current gain ia-ib, the level of output signal Vout of the differential circuit rises to around power source voltage Vcc, whereas the output signal Vout2 from inverter I1 falls to GND potential. After the charging is finished in T12, relationship i70=i75&gt;i76=i71 holds.
During time interval T3, input signal Vin is higher than reference voltage Vref in a stationary state, and the gate-source voltage Vgs of transistor Q71 is higher than the gate-source voltage Vgs of transistor Q70. Thus, current i71 is larger than current i70. Accordingly, the following relationship holds: EQU i70=i75=i76=ia&lt;i71=ic (4),
wherein ic represents the current flowing through transistor Q71 in T3. The current gain in T3 for charging the gate capacitance of inverter I1 is expressed by: EQU i71-i76=ic-ia (5).
The level of output voltage Vout falls from around power source voltage Vcc to around GND potential. Output voltage Yout2 of inverter Ii rises to around power source voltage Vcc. After the discharging, the following relationship holds: EQU i70=i75&lt;i76=i71.
During time interval T2 where input signal Vin rises from L-level to H-level, current i71 gradually increases, and the drain-source voltage Vds of transistor Q76 rises with the discharge of the gate capacitance of inverter I1. Thus, current i76 also increases and Vout falls to L-level after the discharge, and currents i71 and i76 stay at a constant level.
During time interval T4 where input signal Vin falls from H-level to L-level, current i71 gradually decreases, and the drain-source voltage Vds of transistor Q76 falls with the charging of the gate capacitance of inverter 11. Thus, current i76 also decreases and Vout rises to H-level after the charging, and currents i71 and i76 stay at a constant level.
FIG. 5 is a circuit diagram of another conventional differential amplifier for use as an input interface adapted to the LVTTL standard. In the figure, constituent elements similar to those in FIG. 3 are designated by the same or similar reference numerals. In the differential amplifier shown in FIG. 5, N-channel transistor Q80 has a drain connected to both the sources of N-channel transistors Q70 and Q71, a source connected to GND and a gate applied with power source voltage Vcc.
Assuming that W/L dimensions of transistors Q70 and Q75 are equal to W/L dimensions of transistors Q71 and Q76, respectively, when input signal Vin is equal to reference voltage Vref, current equal to half the current i80 flowing through transistor Q80 flows through each of transistors Q70, Q71, Q75 and Q76. For comparing with the differential amplifier of FIG. 3 it is assumed that in FIG. 5 the following relationships hold: EQU i70=i75=i76=i71=ia (6),
and EQU i80=2.times.ia (7)
where Vin=Vref,
FIG. 6 is a timing chart of the differential circuit of FIG. 5. Input signal Mm stays at L-level in T1, rises from L-level to H-level in T2, stays at H-level in T 3, falls from H-level to L-level in T4, and again stays at L-level in T5.
During time intervals T1 and T5 where input signal Vin stays at L-level in a stationary state, input signal Vin is lower than reference voltage Vref. Thus, the gate-source voltage Vgs of transistor Q71 shown in FIG. 5 is lower than the gate-source voltage Vgs of transistor Q70, and accordingly, current i71 is smaller than current i70. The equality of the gate-source voltage Vgs of transistor Q76 and the gate-source voltage Vgs of transistor Q75 signifies the equality of currents i76 and i75. From the relationships (6) and (7), the following relationship is derived: EQU i70=i75=i76=2.times.ia-ib&gt;i71=ib (8),
wherein ib is a constant current.
The current gain charging the gate capacitance of inverter I1 is then expressed by: EQU i76-i71=(2.times.ia-ib)-ib=2(ia-ib) (9).
As shown in FIG. 6, the level of output signal Vout in T1 and T5 is around power source voltage Vcc, and the output voltage of inverter I1 is around GND potential. After the charging, relationship i70=i75&gt;i76=i71 holds. Comparing relationship (9) with relationship (3), it is understood that the differential amplifier of FIG. 5 achieves a current gain (or charging current) which is twice the current gain of the differential amplifier of FIG. 3. In other words, output signal Vout of the differential amplifier of FIG. 5 changes to H-level in a higher speed by double compared to the differential circuit of FIG. 3.
When input signal Mm of FIG. 6 is higher than reference voltage Vref in a stationary state, the gate-source voltage Vgs of transistor Q71 is higher than the gate-source voltage Vgs of transistor Q70, and thus i71&gt; i70. Accordingly, contrary to relationship (8), the following relationship holds: EQU i70=i75=i76=2.times.ia-ic&lt;i71=ic (10).
The current gain for charging the gate capacitance of inverter I1 is expressed by: EQU i71-i76=ic-(2.times.ia-ic)=2(ic-ia) (11).
The level of output voltage Vout falls from around power source voltage Vcc to around GND potential. Output voltage Vout2 of inverter I1 rises to around power source voltage Vcc. After the discharging, relationship i70=i75&lt;i76=i71 holds. Comparing relationship (11) with relationship (5), it is understood that the differential amplifier of FIG. 5 has a discharging current which is twice the discharging current of the differential amplifier of FIG. 3. In other words, output signal Vout of the differential amplifier of FIG. 5 changes to L-level in a higher speed by double compared to the differential circuit of FIG. 3.
During transient time interval T2 where input signal Vin rises L-level to H-level, current i71 gradually increases, and the drain-source voltage Vds of transistor Q76 rises with the discharge of the gate capacitance of inverter I1. At this stage, the current flowing through transistor Q80 is substantially constant, and currents i71 and i75 flowing through transistors Q70 and Q75 decrease. After the discharging, output voltage Vout falls to L-level, and currents i71 and i76 are equal to currents i70 and i75, respectively.
During transient time interval where input signal Mm falls from H-level to L-level, current i71 gradually decreases. At this stage, the substantially constant current flowing through transistor Q80 raises currents i70 and i75 as well as i76. The drain-source voltage Vds of transistor Q76 decreases with the charging of the gate capacitance of inverter I1. Thus, current i76 also decreases and output voltage Vout rises to H-level after the charging. Currents i71 and i76, and currents i70 and i75 reach respective constant levels.
The conventional differential amplifiers shown in FIGS. 3 and 5 involve a problem in that current dissipation increases when external power source voltage Vcc and external input reference Vref change.
Specifically, in the LVTTL standard, as shown in FIG. 1, even if power source voltage Vcc changes, the input level stays at 0.8 volts to 2.0 volts. On the other hand, in the SSTL standard, as shown in FIG. 2, external reference voltage Vref is specified as Vcc.times.0.45 based on external source voltage Vcc. Accordingly, if 2.9 volts.ltoreq.Vcc:23 3.7 volts is assured for the operational margin of a memory device, external reference voltage Vref varies within the range of about 1.3 volts.ltoreq.Vref.ltoreq.1.7 volts.
In the conventional differential amplifier shown in Fig. 5, external source voltage Vcc input to the gate of transistor Q80 and external reference voltage Vref input to the gate of transistor Q70 raise current dissipation when these external power source voltage Vcc and external reference voltage Vref increase.
Similarly, in the conventional differential amplifier shown in FIG. 3, when Vcc and Vref rise, current dissipation generally increases, although the differential amplifier is capable of suppressing overall current dissipation. Specifically, since transistor Q70 acting as a constant current source and transistor Q75 acting another constant current source may have gate length and gate width independently from each other, it is possible to reduce the current flowing through transistor Q70 without changing the ratio between current drivabilities of transistor Q70 and transistor Q75 as by reducing gate widths W of transistors Q70 and Q75 and increasing gate lengths L thereof to suppress the overall current dissipation.
However, such a configuration employed in the conventional differential circuit of FIG. 3 involves a problem in that the current gain is smaller than that of the differential amplifier of FIG. 5. The smaller current gain involves lower operational speed because the time period for the signal change in the differential circuit is determined by the current gain for charging and discharging the gate capacitance of inverter I1.